3i Infotech Papers: Sample Questions 345 - 347 of 1245

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Question number: 345

» Operating System » Unix

Essay Question▾

Describe in Detail

What do you mean by u-area (user area) or u-block?

Explanation

UNIX maintains the information about a process in two areas- process table and the u-area. U-area:

  • The user area of a process is located at the upper end of the process address space and accessible only when running in kernel mode.

  • Contains the private data that is manipulated only the kernel.

  • This is the local to the process; each process is allocated a u-area.

  • When a process is created it is the required small temporary memory to start execution.

  • Temporary private area used only by kernel to control and execute process.

Question number: 346

» Languages » C & C Plus Plus

Short Answer Question▾

Write in Short

  1. int imain()
  2. {
  3.     int t;for ( t=4;scanf("%d",&i)-t;printf("%d ",i)) printf("%d--",t--);
  4. }

If the inputs are 0,1, 2,3 find the output

Explanation

4–0

3–1

2–2

In the program

Table shows the program

Table shows the program

int i;

Define the global integer variable i.

int t;

Define the integer variable t in main class.

for (t = 4; scanf (“%d”, &i) -t; printf (“%d ”, i) )

Given the for loop

Using the input values of 0,1, 2,3 for ‘scanf’ x = scanf (“%d”, &i) -t the values during execution will be,

Table shows the program

Table shows the program

t

i

x

4

0

-4

3

1

-2

2

2

0

Question number: 347

» Basic CS » Operating System

Essay Question▾

Describe in Detail

What is the translation look aside Buffer?

Explanation

Understanding of translation look-aside buffers.

Understanding of Translation Look-Aside Buffers.

Understanding of translation look-aside buffers.

  • Every time the CPU accesses virtual memory, a virtual address translated to the corresponding physical address.

  • Page table contains translations from virtual address to physical address.

  • TLB is a hardware cache that stores recent translation of virtual memory to physical addresses for faster retrieval- part of the chip’s memory management unit.

  • TLB can reside between the CPU and the CPU cache, between CPU cache and the main memory or between different levels of the multi-level cache.

  • Present inside memory management hardware- in processor that utilizes paged or segment virtual memory.

  • Without TLB every virtual memory reference will cause 2 physical memory accesses one to fetch appropriate page table entry, and fetch the desired data.

Cache Thrash

  • Transaction look aside buffer suffers performance issues from multitasking and code errors.

  • Performance degradation is called a cache thrash.