Basic CS-Operating System [3i Infotech Placement]: Sample Questions 24 - 25 of 89

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Question 24

Operating System

Describe in Detail


What is the translation look aside Buffer?


Understanding of Translation Look-Aside Buffers
  • Every time the CPU accesses virtual memory, a virtual address translated to the corresponding physical address.
  • Page table contains translations from virtual address to physical address.
  • TLB is a hardware cache that stores recent translation of virtual memory to physical addresses for faster retrieval- part of the chip՚s memory management unit.
  • TLB can reside between the CPU and the CPU cache, between CPU cache and the main memory or between different levels of the multi-level cache.
  • Present inside memory management hardware- in processor that utilizes paged or segment virtual memory.
  • Without TLB every virtual memory reference will cause 2 physical memory accesses one to fetch appropriate page table entry, and fetch the desired data.

Cache Thrash

  • Transaction look aside buffer suffers performance issues from multitasking and code errors.
  • Performance degradation is called a cache thrash.

Question 25

Operating System

Write in Short

Short Answer▾

Paging is a memory management function, while multiprogramming is a processor management function, are the two interdependent?


  • Yes, paging and multiprogramming are independent.
  • Multiprogramming requires large memory for many processors, virtual memory and paging provide nearly infinite memory. Paging divides address space into smaller segments stored in secondary storage.
  • Moreover, main memory is limited and multiprogramming necessitates multiple working sets in the RAM. Intelligent memory management may thus improve performance.

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